1. Field of the Invention
This invention relates generally to the generation of a timing model for a digital logic circuit, and more particularly, to the generation of a timing model which abstracts the timing constraints for latches internal to the digital logic circuit.
2. Description of the Related Art
As the result of the continuous development of new technologies, particularly in the areas of semiconductor processing, integrated circuits are becoming increasingly more complex and operate at ever faster speeds. For example, the development of semiconductor processes such as xe2x80x9cdeep submicronxe2x80x9d processing has reduced manufacturable circuit dimensions to less than a third of a micron, making it feasible to place more than a million logic gates on a single integrated circuit. With these capabilities, memory, CPU, graphics, communications, specialized functions, etc., may be integrated onto a single chip, creating a xe2x80x9csystem on a chip.xe2x80x9d These advances in semiconductor processing have also led to the emergence of state of the art foundries whose primary expertise is the fabrication of integrated circuits. These foundries typically are not extensively involved in the chip design process and thus can devote their full attention to streamlining and further developing the fabrication process. As a result, the time required to fabricate integrated circuits has fallen steadily and is now on the order of several weeks. This, in turn, has pressured chip designers to complete their design tasks in ever shorter periods of time, resulting in shorter overall product cycles for integrated circuits. In short, advances in semiconductor processing have resulted in increasingly complex chips which must be designed in ever shorter time periods.
To meet this challenge, chip designers are increasingly relying on a hierarchical approach to designing chips. In this approach, a complex chip is segmented into a number of component circuits, each of which may be further segmented into subcomponents, and so on. For example, an integrated circuit containing a xe2x80x9csystem on a chipxe2x80x9d is segmented into a memory component, a CPU component, a graphics component, etc. The CPU component may be further subdivided into ALU, control logic, cache, etc. Likewise, the memory component may be further subdivided into a basic memory cell which is replicated many times, control logic, etc. Dividing a complex chip into a number of simpler circuits achieves several purposes. First, the hierarchical approach provides a systematic approach to designing complex chips. Second, designing each of the components is a more manageable task than designing the entire chip at once. Third, the design time for the chip is reduced because, to some degree, all of the components may be designed in parallel.
It is also becoming increasingly popular to purchase or license some or all of these components from third parties who have previously designed the component, rather than designing the components from scratch. Such circuit components are often referred to as xe2x80x9cIP blocksxe2x80x9d or xe2x80x9cIP cores,xe2x80x9d with the third party being an xe2x80x9cIP provider.xe2x80x9d Here, xe2x80x9cIPxe2x80x9d stands for intellectual property. For example, in a system on a chip, the CPU component may be a RISC processor licensed from MIPS or ARM, and the memory component may be licensed from RAMBUS.
The IP approach typically results in faster design times and often also lower cost. The faster design time results because integrating an IP block into a chip typically requires less time than designing the block from scratch. The lower cost results because the IP provider typically has more expertise in his circuit specialty and so is more efficient in designing the IP block and because the cost of developing the IP block may be spread overall of the IP provider""s customers rather than borne by a single organization. As a result, the IP approach is particularly suited for consumer electronics, which are typically characterized by a high degree of price sensitivity, high volumes, and short product cycles. Recent activity in developing industry standards for interconnecting IP blocks is further encouraging this type of activity.
The hierarchical approach, however, often requires the generation of models, typically a functional model and a timing model, of each of the components during the design process. The functional model describes the function of the component, such as the logic or state machine behavior of the component. The timing model describes timing aspects of the component, such as the propagation delay through the component and/or timing constraints for latches internal to the component. Each latch typically will have its own timing constraints, such as set-up and hold requirements, which must be met in order for the latch to operate properly. These models preferably are xe2x80x9cblack-boxxe2x80x9d models, meaning that the model would provide enough information to allow correct interfacing of the component with other components and to allow correct integration of the component into the chip but without disclosing the internal design of the component.
Black-box models are preferred because for most uses of these models, knowledge of the internal design of the components is not necessary and usually is undesirable. For example, in the case of an IP provider, the internal design of the component is the proprietary information which the IP provider sells. If the internal design were generally known, the IP provider""s business essentially would be ended. Hence, an IP provider would like to provide functional and timing models of his IP block which provide enough information for his customer to design with the IP block but which reveal as little about the internal design as possible. In other words, he prefers a black-box model of the IP block. Furthermore, black-box models are generally simpler than models which require details of the internal design and thus have the added benefit of requiring less computational horsepower during the design process. However, generating a black-box model which abstracts the timing constraints for the latches internal to a circuit has been problematic.
In a traditional approach, the entire internal design of the component is provided, typically as a netlist, in order to allow the chip designer to determine whether the timing constraints for the internal latches are met. This, however, is problematic because the entire internal design is accessible by the chip designer which is exactly what the IP provider wishes to avoid. In addition, a complex IP block may have thousands of latches and this approach requires that the timing constraints of each latch be checked on an individual basis, which is time-consuming.
In an alternate approach, termed the xe2x80x9cgray-boxxe2x80x9d model, a modified version of the internal design is provided for modeling purposes. The internal design is divided into regions of combinational logic and latches. Latches are connected to each other via the combinational logic regions. Each of the combinational logic regions is reduced to a black-box which models the propagation delay through the region but without any specifics regarding the internal design of the region. The gray-box model then consists of the actual latches interconnected by the black-box models of the combinational logic regions. This approach is an improvement over the traditional approach but still suffers from the basic drawbacks of the traditional approach. In particular, the gray-box model still reveals a significant amount of information about the internal design of the IP block since the clocking and placement of all latches is still apparent. In addition, the time-consuming task of checking the timing constraints for each latch on an individual basis still exists.
Thus, there is a need for a timing model which abstracts the timing constraints for latches internal to a circuit while minimizing the amount of information about the internal design of the circuit which is included in the model. There is also a need for such a timing model which further allows the timing constraints for the internal latches to be checked in a time-efficient manner.
In accordance with the present invention, a computer-implemented method for generating a clock characterization model of a digital logic circuit is implemented in a computer automated design system. The digital logic circuit includes a plurality of interconnected latches and combinational logic circuits. The method includes the following steps. Timing information for the latches and for the combinational logic circuits is received, and preferably includes propagation models for the combinational logic and both propagation models and timing constraints (such as set-up and hold requirements) for the latches. A description of a class of clock scheme for clocking the digital logic circuit is also received. The clock scheme class preferably is defined solely by the number of clocks in the clock scheme and the relative ordering of their clock edges. Clock parameters for parameterizing the clock scheme class are selected. Timing constraint expressions based on the received timing information and expressed in terms of the clock parameters are derived for signal paths between latches within the digital logic circuit. In a preferred embodiment, the timing constraint expressions are based on set-up, hold, loop, and maximum transparency requirements for transparent signal paths within the digital logic circuit. The timing constraint expressions are combined to define a region of feasible clock operation for the clock scheme class.
The present invention is particularly advantageous because the clock characterization model abstracts the timing constraints which are internal to the digital logic circuit. Thus, for example, these timing constraints may be checked by referring to the clock characterization model rather than the actual circuit design of the circuit. This preserves the propriety of the actual circuit design. In addition, the clock characterization model is simpler than other alternatives for modeling the internal timing constraints of a circuit. This results in time savings when checking the internal timing constraints for design faults.
In another aspect of the invention, a computer readable medium stores a clock characterization modeler for instructing a processor to execute the above method.
In another aspect of the invention, a method for using the clock characterization model to design a first digital logic circuit which includes a second digital logic circuit includes the following steps A clock characterization model for the second digital logic circuit is received. A trial clock scheme for the first digital logic circuit is selected and it is determined whether the trial clock scheme falls within the region of feasible clock operation defined by the clock characterization model.